SoC Physical Design Verification Engineer
Summary
Posted: Nov 18, 2024
Role Number:200575861
At Apple, we work every single day to craft products that enrich people's lives! Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, youll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). Youll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining our group means youll be responsible for crafting and building the technology that fuels Apples devices. Together, we will enable our customers to do all the things they love with their devices!
In this highly visible role, you will be a part of a critical team responsible for physical verification of an SOC.
Description
Description
- As a member of our physical design team, you will perform various types of physical verification checks such as LVS, DRC, ANT, and ESD at the chip and block level.
- You will collaborate with the CAD/Technology teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout.
- You will lead schedules and support cross-functional engineering efforts.
- You will work on padring, bump, RDL design, and working with the package and floorplan teams.
Minimum Qualifications
Minimum Qualifications
Minimum BS in Electrical/Electronics/Computer Engineering or related field.
3+ years of relevant industry experience.
Direct experience with physical verification flows and methodology through tape out execution.
Knowledge of all aspects of ASIC physical design.
Knowledge of place and route design flow methodology.
Scripting skills to debug flow related issues and make enhancements as appropriate.
Direct work experience with industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc.
Full chip tapeout experience with a track record of successful signoff.
Key Qualifications
Key Qualifications
Preferred Qualifications
Preferred Qualifications
MS in Electrical/Electronics/Computer Engineering or related field.
Proficient scripting skills and automation experience.
Layout or floorplan design experience.
Physical design verification and debug experience including mixed signal and digital IP integrations at block and full-chip hierarchies.
Education & Experience
Education & Experience
Additional Requirements
Additional Requirements
More
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
Apply Now
Posted: Nov 18, 2024
Role Number:200575861
At Apple, we work every single day to craft products that enrich people's lives! Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, youll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). Youll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining our group means youll be responsible for crafting and building the technology that fuels Apples devices. Together, we will enable our customers to do all the things they love with their devices!
In this highly visible role, you will be a part of a critical team responsible for physical verification of an SOC.
Description
Description
- As a member of our physical design team, you will perform various types of physical verification checks such as LVS, DRC, ANT, and ESD at the chip and block level.
- You will collaborate with the CAD/Technology teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout.
- You will lead schedules and support cross-functional engineering efforts.
- You will work on padring, bump, RDL design, and working with the package and floorplan teams.
Minimum Qualifications
Minimum Qualifications
Minimum BS in Electrical/Electronics/Computer Engineering or related field.
3+ years of relevant industry experience.
Direct experience with physical verification flows and methodology through tape out execution.
Knowledge of all aspects of ASIC physical design.
Knowledge of place and route design flow methodology.
Scripting skills to debug flow related issues and make enhancements as appropriate.
Direct work experience with industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc.
Full chip tapeout experience with a track record of successful signoff.
Key Qualifications
Key Qualifications
Preferred Qualifications
Preferred Qualifications
MS in Electrical/Electronics/Computer Engineering or related field.
Proficient scripting skills and automation experience.
Layout or floorplan design experience.
Physical design verification and debug experience including mixed signal and digital IP integrations at block and full-chip hierarchies.
Education & Experience
Education & Experience
Additional Requirements
Additional Requirements
More
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
Apply Now