RISC-V AI / HPC & Agentic Software Engineering Lead
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
Tenstorrent is building next-generation RISC-V CPUs optimized for AI, high-performance computing, and emerging autonomous AI systems. As the RISC-V AI / HPC & Agentic Software Engineering Lead, you will operate at the hardwareâsoftware boundary, enabling AI, HPC, and agentic AI software stacks on Tenstorrentâs RISC-V processors. This role is responsible for integrating and optimizing Tenstorrentâs LLK (Low-Level Kernel) infrastructure for CPU execution, while leading the bring-up of a RISC-V-native agentic AI software stack â including runtime orchestration, distributed execution frameworks, memory systems, and developer tools required for goal-driven AI systems. You will work closely with CPU architects, microarchitecture teams, compiler engineers, and AI kernel developers to ensure tight alignment between software capabilities and RISC-V architectural features.
This role is remote, based out of North America.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
⢠A systems-oriented software engineer with deep experience in HPC and AI software stacks.
⢠Experienced with distributed AI systems, orchestration frameworks, or agentic AI architectures.
⢠Comfortable working close to hardware and instruction-level programming.
⢠Skilled at translating performance targets into architectural and software requirements.
⢠Experienced in runtime systems, profiling, and low-level optimization.
⢠Motivated by hardwareâsoftware co-design and scaling next-generation AI infrastructure.
What We Need
⢠Strong background in HPC and AI software development.
⢠Solid understanding of RISC-V architecture (ISA, extensions, micro-architectural implications).
⢠Proficiency in C/C++ and systems programming.
⢠Experience optimizing performance-critical code paths.
⢠Experience with agentic AI frameworks, distributed execution systems, or orchestration platforms.
⢠Familiarity with compiler toolchains (LLVM, GCC).
⢠Experience with vectorization, custom ISA extensions, or accelerator integration.
What You Will Learn
⢠How AI and agentic workloads map to RISC-V microarchitecture.
⢠Custom ISA extension design for AI acceleration.
⢠End-to-end HPC/AI/agentic stack integration.
⢠Runtime orchestration for distributed AI systems.
⢠Hardwareâsoftware co-design for scalable AI-native CPU platforms.
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
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Tenstorrent is building next-generation RISC-V CPUs optimized for AI, high-performance computing, and emerging autonomous AI systems. As the RISC-V AI / HPC & Agentic Software Engineering Lead, you will operate at the hardwareâsoftware boundary, enabling AI, HPC, and agentic AI software stacks on Tenstorrentâs RISC-V processors. This role is responsible for integrating and optimizing Tenstorrentâs LLK (Low-Level Kernel) infrastructure for CPU execution, while leading the bring-up of a RISC-V-native agentic AI software stack â including runtime orchestration, distributed execution frameworks, memory systems, and developer tools required for goal-driven AI systems. You will work closely with CPU architects, microarchitecture teams, compiler engineers, and AI kernel developers to ensure tight alignment between software capabilities and RISC-V architectural features.
This role is remote, based out of North America.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
⢠A systems-oriented software engineer with deep experience in HPC and AI software stacks.
⢠Experienced with distributed AI systems, orchestration frameworks, or agentic AI architectures.
⢠Comfortable working close to hardware and instruction-level programming.
⢠Skilled at translating performance targets into architectural and software requirements.
⢠Experienced in runtime systems, profiling, and low-level optimization.
⢠Motivated by hardwareâsoftware co-design and scaling next-generation AI infrastructure.
What We Need
⢠Strong background in HPC and AI software development.
⢠Solid understanding of RISC-V architecture (ISA, extensions, micro-architectural implications).
⢠Proficiency in C/C++ and systems programming.
⢠Experience optimizing performance-critical code paths.
⢠Experience with agentic AI frameworks, distributed execution systems, or orchestration platforms.
⢠Familiarity with compiler toolchains (LLVM, GCC).
⢠Experience with vectorization, custom ISA extensions, or accelerator integration.
What You Will Learn
⢠How AI and agentic workloads map to RISC-V microarchitecture.
⢠Custom ISA extension design for AI acceleration.
⢠End-to-end HPC/AI/agentic stack integration.
⢠Runtime orchestration for distributed AI systems.
⢠Hardwareâsoftware co-design for scalable AI-native CPU platforms.
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Apply tot his job
Apply To this Job